Getting Started with KiCad for Multi-Layer PCB Design

KiCad has come a long way. As someone who spent years working exclusively in OrCAD/Allegro, I was skeptical when I first tried KiCad for a personal project. But KiCad 7+ is genuinely capable of handling multi-layer designs — and the price (free) is hard to argue with for personal projects and small teams.

This guide covers setting up KiCad for a 4-layer PCB design, which is the most common multi-layer configuration for moderately complex designs.

Why Multi-Layer?

Before diving into KiCad specifics, a quick primer on why you’d want more than two layers:

Signal integrity — dedicated ground planes provide low-impedance return paths
Power distribution — dedicated power planes reduce voltage droop
Routing density — more layers = more routing channels = simpler trace routing
EMI reduction — proper layer stacking with ground planes dramatically reduces electromagnetic emissions

For most designs beyond simple breakout boards, a 4-layer stackup is the sweet spot of cost vs. capability.

Setting Up the Layer Stackup

Open your PCB in KiCad’s PCB Editor, then go to Board Setup → Board Stackup → Physical Stackup.

A standard 4-layer stackup looks like this:

Layer 1 (F.Cu)    — Signal / Components
Prepreg            — Dielectric (e.g., 7628, 0.2mm)
Layer 2 (In1.Cu)  — Ground Plane
Core               — Dielectric (e.g., 1.0mm)
Layer 3 (In2.Cu)  — Power Plane
Prepreg            — Dielectric (e.g., 7628, 0.2mm)
Layer 4 (B.Cu)    — Signal / Components

Key stackup principles:

Keep signal layers adjacent to ground planes — this ensures controlled impedance and good return paths
Use a thin prepreg between signal and ground layers — tighter coupling means better signal integrity
The core is typically thicker than prepreg — this gives the board mechanical rigidity

In KiCad, you configure this by clicking “Add Dielectric Layer” and setting the material properties (dielectric constant, thickness, loss tangent).

Design Rules for Multi-Layer Boards

Go to Board Setup → Design Rules → Net Classes to configure your trace widths and clearances.

For a typical 4-layer design with standard manufacturing:

Default Net Class:
  Track Width:    0.15mm (6 mil)
  Clearance:      0.15mm (6 mil)
  Via Size:       0.6mm drill / 0.3mm annular ring

Power Net Class:
  Track Width:    0.3mm (12 mil)
  Clearance:      0.2mm (8 mil)

High-Speed Net Class:
  Track Width:    0.127mm (5 mil)  — for 50Ω impedance on typical stackup
  Clearance:      0.2mm (8 mil)    — wider clearance for crosstalk reduction

Setting Up Custom Design Rules

KiCad supports a custom DRC rules file for more complex constraints. Create a file called custom_rules.kicad_drc in your project directory:

(version 1)

# Minimum annular ring for vias
(rule "Via Annular Ring"
  (condition "A.Type == 'Via'")
  (constraint annular_width (min 0.15mm))
)

# Clearance between high-speed nets
(rule "High Speed Clearance"
  (condition "A.NetClass == 'HighSpeed' && B.NetClass == 'HighSpeed'")
  (constraint clearance (min 0.25mm))
)

# Board edge clearance
(rule "Board Edge Clearance"
  (condition "A.Type == 'Track' || A.Type == 'Via'")
  (constraint edge_clearance (min 0.3mm))
)

Ground Plane Best Practices

When setting up your ground plane (typically Layer 2 / In1.Cu):

Pour a copper zone that covers the entire board area
Assign it to your GND net
Set the zone priority to ensure it fills properly around vias and pads
Avoid splitting the ground plane unless you absolutely need to (split planes create return path discontinuities)

In KiCad, draw a zone outline on the In1.Cu layer:

Right-click → Add Zone → select the In1.Cu layer
Set net to GND
Set clearance to 0.2mm
Set minimum width to 0.15mm
Enable thermal relief for through-hole pads (spoke width: 0.3mm, gap: 0.3mm)

Via Stitching

For multi-layer designs, via stitching connects ground planes on different layers, reducing ground impedance and improving EMI performance:

Place ground vias every 5-10mm around the board perimeter
Add stitching vias near high-speed signal transitions between layers
Place stitching vias near decoupling capacitors to connect them to the ground plane

KiCad doesn’t have automatic via stitching (as of KiCad 7), but you can use the array tool (Ctrl+T after selecting a via) to quickly place a row or grid of stitching vias.

Impedance Control

For controlled impedance traces (USB, DDR, Ethernet, etc.), you need to calculate the correct trace width based on your stackup.

Use an impedance calculator like Saturn PCB Toolkit (free) or KiCad’s built-in calculator (in the standalone Calculator tool):

For a microstrip (outer layer, trace over ground plane):

50Ω single-ended typically needs ~0.12-0.15mm trace width with 0.2mm prepreg

For a stripline (inner layer, trace between two ground planes):

50Ω single-ended typically needs ~0.10-0.12mm trace width

Document your impedance requirements in the fabrication notes so the fab house can adjust trace widths during DFM if needed.

Manufacturing Outputs

When your design is ready for fabrication, generate Gerbers via File → Fabrication Outputs → Gerbers:

For a 4-layer board, you’ll generate:

F.Cu.gbr, In1.Cu.gbr, In2.Cu.gbr, B.Cu.gbr (copper layers)
F.SilkS.gbr, B.SilkS.gbr (silkscreen)
F.Mask.gbr, B.Mask.gbr (solder mask)
F.Paste.gbr, B.Paste.gbr (solder paste stencil)
Edge.Cuts.gbr (board outline)
Drill files (.drl)

Also generate a drill file via File → Fabrication Outputs → Drill Files and include both plated and non-plated hole files.

Final Thoughts

KiCad is more than capable of handling 4-layer (and even 6-8 layer) PCB designs. The key limitations compared to Allegro are in advanced constraint management and high-speed design rule support — but for the vast majority of designs, KiCad does the job well.

Start with a solid stackup, set up your design rules early, and don’t skip the ground plane fundamentals. The rest is routing.